| |
VHDL and Programmable Logic
VHDL is a hardware description language used to design and model digital electronic systems. Its name stands for VHSIC Hardware Description Language, where VHSIC refers to a United States programme on Very High Speed Integrated Circuits. Rather than drawing a circuit gate by gate, an engineer describes the desired behaviour and structure of digital logic in text, which design tools then translate into an actual circuit implementation.
VHDL allows designs to be expressed at different levels of abstraction, from the flow of data and the behaviour of logic over time down to the interconnection of specific components. A description can be simulated to verify that it behaves correctly before any hardware is built, and the same description can then be synthesised into the logic needed to realise it. This separation of design from a particular technology makes VHDL portable and reusable across projects and devices.
The language is closely associated with programmable logic devices, which are chips whose internal logic can be configured by the user rather than being fixed at manufacture. These include simple devices such as PALs (Programmable Array Logic) and PLAs (Programmable Logic Arrays), as well as more complex field-programmable gate arrays (FPGAs). VHDL is also used to design application-specific integrated circuits (ASICs), which are custom chips manufactured for a particular function. By describing logic functions such as AND, OR, NAND, NOR and NOT in a structured way, VHDL lets designers build and test complex digital systems efficiently. Verilog is another widely used hardware description language serving similar purposes.
Frequently asked questions
- What is VHDL used for?
- It is a hardware description language used to design, simulate and synthesise digital circuits, describing their behaviour and structure in text rather than as a schematic.
- What is a programmable logic device?
- It is a chip, such as a PAL, PLA or FPGA, whose internal logic can be configured by the user after manufacture to implement a desired digital function.
- What is the difference between an FPGA and an ASIC?
- An FPGA is a reconfigurable device programmed by the user, while an ASIC is a custom chip manufactured for a specific fixed function. VHDL can be used to design both.
|
|
VHDL
related topic: PIC's |
|
Altera Timing Models |
|
Digital System Design |
|
MAX plus II tutorial |
|
VHDL archive
a collection of free, i.e. public-domain or shareware, VHDL documentation,
models, and tools |
|
VHDL Cookbook
this page contains an online book introducing VHDL |
|
VHDL basic programming elements identifiers, bit strings, data types,
enumeration types, arrays, physical types, records, subtypes, object
declarations, alias, attributes, operators and expressions, access type ,
exercises, signal and signal assignments, signal and variable, inertial delay,
transport delay, signal attributes , resolution functions, signals versus
variables, exercises |
|
VHDL builder
Design Process, Description Styles, Describing Designs, Data Types, Expressions,
Sequential Statements, Concurrent Statements, Register, Multiplexer and
Three-State Inference, Resource Sharing, Writing Circuit Descriptions, VHDL
Compiler Directives |
|
VHDL Design Examples VHDL
Design Examples |
|
VHDL-easy
Description of Syntax and Semantic, Objects and Data Types, Expressions and
Operators, Sequential Statements, Design Units, Structural Modeling, Behavioral
Modeling |
|
VHDL entities, architectures and processes |
|
VHDL entities, architectures and components- describing structure and its
attributes |
|
VHDL Examples |
|
VHDL functions, procedures, packages and libraries |
|
VHDL
reference manual Structure of a VHDL Design Description, Library Units,
Package, Entity, VHDL Architecture, VHDL Configuration, VHDL Statements,
Declaration Statements, Concurrent and Sequential Statements, Data Objects, How
to Write Synthesizable VHDL, How to Control the Implementation of VHDL, VHDL
Datapath Synthesis, How to Manage VHDL Design Hierarchies,
pdf file |
|
VHDL sequential statements |
|
VHDL signals, signal assignments, signal attributes and resolution functions |
|
VHDL simulator for Linux!
VHDL simulator for Linux! |
|
VHDL Syntax Reference |
|
VHDL Tutorial VHDL Tutorial,
Basic Logic Gates, Combinational Logic Design, Typical Combinatinal Logic
Components Latch and Flip-Flops, Sequential Logic Design, Typical Sequential
Logic Components, Custom Single-Purpose Processor Design, General-Purpose
Processor Design |
|
VHDL Tutorial
pdf file |
|
|
Home
|
Site Map
|
Email: support[at]karadimov.info
Last updated on:
2026-06-24
|
Copyright © 2011-2021 Educypedia.
https://educypedia.org
|
| |
|
|