Programmable logic devices

Programmable logic devices (PLDs) are integrated circuits whose internal connections can be configured by the user to implement a chosen digital function, rather than being fixed during manufacture. They occupy the middle ground between standard fixed-function logic chips and full custom integrated circuits, letting a designer build complex logic without the cost and delay of a dedicated chip. The earliest forms were based on arrays of AND and OR gates whose connections are set by a pattern of programmable links.

The programmable logic array (PLA) has both a programmable AND plane and a programmable OR plane, giving great flexibility. The programmable array logic (PAL) simplifies this by making only the AND plane programmable while the OR plane is fixed, which lowers cost and improves speed for many common functions. Adding flip-flops to the outputs allows these devices to implement sequential logic such as counters and state machines.

As capacity grew, larger architectures appeared. A complex programmable logic device (CPLD) combines several PAL-like blocks with a programmable interconnect, offering predictable timing and non-volatile configuration. The field-programmable gate array (FPGA) takes a different approach, using a large grid of small configurable logic blocks linked by a flexible routing network, often with embedded memory and arithmetic units. FPGAs can hold very large designs and are usually configured from an external memory at power-up. Designs for all these devices are normally described in a hardware description language and compiled by software into the configuration pattern.

Frequently asked questions

What is the difference between a PLA and a PAL?

A PLA has programmable AND and OR planes, while a PAL keeps the OR plane fixed and only the AND plane programmable, which makes it cheaper and faster for many designs.

How does an FPGA differ from a CPLD?

An FPGA uses many small logic blocks and flexible routing to hold very large designs, whereas a CPLD has fewer, larger blocks with more predictable timing and is usually non-volatile.

How are programmable logic devices designed?

Designers typically write the logic in a hardware description language, then software synthesises it into the configuration pattern loaded into the device.