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Chip Packaging Technology

Chip packaging is the stage that turns a fragile silicon die into a finished component that can be handled, mounted on a circuit board, and connected to other parts. The bare die that comes from the fabrication process is tiny and easily damaged, and its electrical contacts are far too small to wire directly. The package protects the die from moisture, dust and mechanical stress, carries the heat it produces away to the surroundings, and provides robust connections of a practical size.

Inside a typical package the die is attached to a base or substrate, and its contact pads are joined to the package’s leads. This connection is made either with fine bond wires running from the pad to each lead, or, in flip-chip designs, by turning the die over and joining it through small solder bumps directly to the substrate. The assembly is then sealed in plastic or ceramic to form the body of the component.

Many package styles exist to suit different needs. Through-hole packages have leads that pass through holes in the board, while surface-mount packages such as the quad flat package (QFP) and small-outline package (SOP) have leads that solder to pads on the surface. Ball grid array (BGA) packages place an array of solder balls under the body, allowing far more connections in a small area. Chip-scale packages (CSP) are barely larger than the die itself, helping to shrink modern electronics.

Frequently asked questions

Why does a chip need a package?
The bare silicon die is fragile and its contacts are far too small to use directly. The package protects it, removes heat, and provides connections of a practical size for mounting on a board.
What is a ball grid array?
A BGA is a package with an array of solder balls on its underside instead of leads around the edge, allowing many more connections to fit in a small footprint.
What is flip-chip bonding?
In flip-chip bonding the die is turned upside down and joined to the substrate through small solder bumps, rather than with bond wires, which shortens the connections.





Chip packaging technology  related topics: Soldering, Digital: technology, PCB fabrication
Applications for Silicone Materials in IC Packaging pdf file
BGA Packages BGA Packages, pdf file
CSP Socket Primer
Chip packaging technology Wafer Level Chip Size Packaging Technology, pdf file
Dual In-Line Package Ceramic Dual-in-Line Package (Cerdip), pdf file
IC logos IC logos, Identification of IC manufacturer by logo
IC Package Families
IC Package information DIP (Dual-in-line Package), SDIP (Skinny Dual-in-line Package), SDIP (Shrink Dual-in-line Package), ZIP (Zig-Zag In-line Package), SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin Small Outline Package), QFP (Quad Flat Package), LQFP (Low Profile Quad Flat Package), TQFP (Thin Quad Flat Package), SOJ (Small Outline J-lead), QFJ (Quad Flat J-lead), BGA (Ball Grid Array), FBGA (Fine Ball Grid Array), FLGA (Fine Land Grid Array), W-CSP (Wafer-level Chip Size Package), TCP (Tape Carrier Package)
IC packages data handbook Through-Hole Mount Packages, Surface Mount Packages,
IC Packaging Packaging the IC chip is a necessary step in the manufacturing process because the IC chips are small, fragile, susceptible to environmental damage, and too difficult to handle by the IC users. In addition, the package acts as a mechanism to “spread apart” the connections from the tight pitch (center to center spacing of two parallel conductors) on the IC die to the relatively wide pitch required by the Printed Circuit Board (PCB) manufacturer, pdf file
IC packaging information IC packaging information, pdf file
IC packaging technology ppt file
IC packaging technology IC packaging technology, Area Array package, FBGA/FLGA, T-BGA, Enhanced P-BGA, P-BGA, Flat package, QFP, LQFP, TQFP, TSOP, TSSOP, HSOF, SOP, SSOP, SOJ, DIP, SIP, SZIP, SDIPIC packaging technology, pdf file
Intel packaging technology An overview of package families, including package attributes, package types, and a package selection guide: FCBGA, PBGA MDDS, BGA, PGA MDDS, QFP MDDS, SOP MDDS, CSP, Chip Scale Packaging, Plastic Ball Grid Array package technology, Plastic Pin Grid Array package technology, and its physical structure, Tape Carrier Package, ESD/EOS precautions, Physical constants of IC package materials, pdf file
Microelectronic design Silicon microelectronic fabrication process and packaging
Package information SAMSUNG Semiconductor products
Package outline drawings pdf file
Package Terminology
Package outline drawings BGA, DBS, DIL, DIP, DQFN, DHVQFN, DHXQFN, HBCC, HDIP, HSOP, HTSSOP, HUQFN, HVQFN, HVSON, HWQFN, HWSON, HXQFN, HXSON, LFBGA, LQFP, MicroPak™, NanoStar™, PicoGate, PLCC, QFP, QSOP, RBS, SIL, SO, SSOP-II, SSOP-III, TFBGA, TQFP, TSSOP-I, TSSOP-II, TVSOP, VFBGA, VSO, VSSOP, XQFN, XSON
Packages Index BGA (Ball Grid Array), CBGA (Ceramic), FCBGA, PBGA (Plastic), SBGA (w/Heatsink), CSP (Chip Scale Package), CSP BGA (Ball Grid Array), LFCSP (LeadFrame), LGA (Land Grid Array), Tape CSP BGA, WLCSP (Wafer Level), DIP (Dual Inline Package), CerDIP (Ceramic), CerDIP - Side or Bottom Brazed, DIP Gullwing Leads, Metal or Hybrid DIP, PDIP (Plastic), FlatPack, Ceramic Flat Package, QFP (Quad Flat Pack), CQFP (Ceramic), LQFP 1.4mm thick, LQFP w/heat sink, MQFP, MQFP - Thermally Enhanced, TQFP (Thin, 1.0mm), TQFP - Thermally Enhanced, SIP (Single Inline Package), SIP Horizontal Leads, SIP Vertical Leads, SOIC (Small Outline IC), PSOP (SOIC w/heatslug), SOIC (Narrow), SOIC (Wide), SOP (Small Outline Package), MSOP (micro-SOP), QSOP (25mil pitch), SSOP (Shrink SO), Thermally Enhanced [PSOP/2], TSSOP (Thin, 1.2mm), TSSOP_EP, SOT (Small Outline Transistor), SC-70, SOT-143, SOT-223, SOT-23, SOT-66, SOT-89, TSOT-23 (Thin, 0.9mm)
Semiconductor packaging pdf file
Semiconductor Packaging Assembly Technology pdf file
SMD marking codes SMD codebook: This HTML book is designed to provide an easy means of device identification. It lists well over 3,900 device codes in alphabetical order, together with type numbers, device characteristics or equivalents and pinout information
S M N P introduction to surface mount nomenclature and packaging, pdf file
Thermal and electrical characteristics of semiconductor packages Mechanism of heat dissipation, Classification of electrical noise, Four major influential factors in thermal resistance, Different electrical requirements for different applications, Thermal design of a package, Electrical characteristics of each package

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